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1 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation sp6644/6645 single/dual alkaline cell, high efficiency boost dc-dc regulator 90ma output current at 1.3v input 190ma output current at 2.6v input +2v to +5.5v output range 0.88v guaranteed start-up 92% high efficiency 1.6 a quiescent supply current at v batt reverse battery protection internal synchronous rectifier 5na logic controlled shutdown current from v batt low-battery detection active low output gnd fb lx v batt 47 f 47 f r lim +3.3v out shdn 22 h 0.7a 0.88v to 3.3v input sp6644 sp6645 battlo v out description the sp6644/6645 devices are high-efficiency, low-power step-up dc-dc converters ideal for single or dual alkaline cell applications such as pagers, remote controls, pointing devices, medical monitors, and other low-power portable end products. designers can control the sp6644 device with an active low shutdown input. the sp6644 device features an active low output for batteries below +1.0v. the sp6645 device features an active low output for batteries below +2.0v. both devices contain a 0.8 ? synchronous rectifier, a 0.5 ? n-channel mosfet power switch, an internal voltage reference, circuitry for pulse- frequency-modulation, and an under voltage comparator. the output voltage for the sp6644/6645 devices is preset to +3.3v + 4% or can be adjusted from +2v to +5.5v by manipulating two external resistors typical application circuit sp6644 sp6645 8 pin msop 8 7 6 4 v out lx gnd fb v bat battl0 r lim shdn 1 2 3 4 now available in lead free packaging small 8 pin msop package no external fets flexibility to optimize inductor type with programmable peak current control
2 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v batt to gnd.............................................-0.3 to 6.0v v out to gnd..............................................-0.3 to 6.0v lx, shdn, fb, battlo, to gnd.............-0.3 to 6.0v reverse battery current, t amb =+25?c.............220ma (note 1) v batt forward current............................................0.5a v out , lx current......................................................1a storage temperature range............-65?c to +165?c lead temperature (soldering 10s)..................+300?c operating temperature.......................-40?c to +85?c power dissipation per package 8-pin soic (derate 4.85mw/ o c above +70 o c) ..........390mw v batt = v shdn = 1.3v, i load = 0ma, fb = gnd, t amb = -40 o c to +85 o c, and typical values are at t amb = +25 o c unless otherwise noted. electrical characteristics r e t e m a r a p. n i m. p y t. x a ms t i n u ? ? ? ? ? s n o i t i d n o c , e g a t l o v t u p n i g n i t a r e p o m u m i x a m v ) x a m ( t t a b 3 . 3v ? ? ? ? ? v , e g a t l o v t u p n i p u - t r a t s t t a b 2 8 . 01 . 1v ? ? ? ? ? r l k 3 = ? , v , e g a t l o v t u p n i p u - t r a t s t t a b t n e i c i f f e o c e r u t a r e p m e t 1 - c v m e g a t l o v t u p n i n d h s v l i v h i 0 8 5 1% v f o % t t a b v f o % t t a b t n e r r u c t u p n i n d h s10 0 1a n ? ? ? ? ? t n e r r u c t u p n i b f10 0 1a n ? ? ? ? ? v b f , v 3 . 1 = v , e g a t l o v t e s b f b f 5 1 2 . 12 6 2 . 19 0 3 . 1v ? ? ? ? ? k c a b d e e f l a n r e t x e e g a t l o v p i r t g n i l l a f o l t t a b4 9 . 0 8 8 . 1 0 0 . 1 0 0 . 2 6 0 . 1 2 1 . 2 v ? ? ? ? ? v , 4 4 6 6 p s t u o v 3 . 3 = v , 5 4 6 6 p s t u o v 3 . 3 = v , e g a t l o v t u p t u o t u o 6 1 . 30 3 . 34 4 . 3v ? ? ? ? ? v b f v 1 . 0 < e g n a r e g a t l o v t u p t u o0 . 25 . 5v ? ? ? ? ? k c a b d e e f l a n r e t x e e c n a t s i s e r - n o l e n n a h c - n5 . 00 . 1 ? v t u o v 3 . 3 = e c n a t s i s e r - n o l e n n a h c - p8 . 06 . 1 ? v t u o v 3 . 3 = absolute maximum ratings
3 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation v batt = v shdn = 1.3v, i load = 0ma, fb = gnd, t amb = -40 o c to +85 o c, and typical values are at t amb = +25 o c unless otherwise noted. note 1: the reverse battery current is measured from the typical operating circuit's input terminal to gnd when the battery is connected backward. a reverse current of 220ma will not exceed package dissipation limits but, if left for an extended time (more than 10 minutes), may degrade performance. note 2: specifications to -40 o c are guaranteed by design, not production tested. note 3: inductor peak current where . i peak = 1400 r lim r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c v o t n i t n e r r u c t n e c s e i u q t u o i , t u o q 0 50 8 a ? ? ? ? ? v t u o v 5 . 3 = v o t n i t n e r r u c t n e c s e i u q t t a b i , t t a b q 6 . 10 . 3 a ? ? ? ? ? v t t a b v 0 . 1 = v o t n i t n e r r u c n w o d t u h s t u o i , t u o n d h s 1 0 0 . 05 . 0 a ? ? ? ? ? v t u o v , v 5 . 3 = n d h s v 0 - v o t n i t n e r r u c n w o d t u h s t t a b i , t t a b n d h s 5 0 0 . 01 . 0 a ? ? ? ? ? v t t a b v , v 0 . 1 = n d h s v 0 - v , o l t t a b r o f e g a t l o v t u p t u o w o l l o 4 . 0v ? ? ? ? ? v t t a b v , v 9 . 0 = t u o i , v 3 . 3 + = k n i s a m 1 = o l t t a b r o f t n e r r u c e g a k a e l1 a ? ? ? ? ? v t t a b v , v 6 . 2 = o l t t a b v 5 . 3 = y c n e i c i f f e9 8% ? ? ? ? ? i d a o l v , a m 0 5 1 = t t a b v 6 . 2 = i , t n e r r u c k a e p r o t c u d n i k a e p 5 7 20 5 30 0 4a m ? ? ? ? ? r m i l k 5 = ? 3 e t o n , ) o l v u ( t u o - k c o l e g a t l o v r e d n u0 0 5 . 00 2 7 . 0v ? ? ? ? ? electrical characteristics
4 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation refer to the circuit in figure 28, t amb = +25 o c unless otherwise noted. figure 1. efficiency vs. output current (vout=3.3v), rlim=2.5k, li=22uh sumida cd43 figure 2. efficiency vs. output current (v out =3.3v), rlim=5k, li=22 h sumida cd43 figure 3. efficiency vs. output current (vout=3.3v), rlim=2.5k, li=22uh sumida cdrh5d18 low profile figure 4. efficiency vs. output current (vout=3.3v), rlim=5k, li=100 h sumida cd54 figure 5. efficiency vs. output current (vout=5v), rlim=2.5k, li=22uh sumida cd43, refer to figure 29, r1=499k, r2=169k figure 6. efficiency vs. output current (vout=5v), rlim=5k, li=22uh sumida cd43, refer to figure 29, r1=499k, r2=169k figure 8. line/load rejection vs. output current (vout=3.3v), rlim=5k, li=22uh sumida cd43 figure 7. line/load rejection vs. output current (vout=3.3v), rlim=2.5k, li=22uh sumida cd43 40 50 60 70 80 90 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) vb=1.0v vb=1.3v vb=2.0v vb=2.6v vb=3.2v efficiency (%) 40 50 60 70 80 90 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) vb=1.0v vb=1.3v vb=2.0v vb=2.6v vb=3.2v efficiency (%) 40 50 60 70 80 90 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) vb=1.0v vb=1.3v vb=2.0v vb=2.6v vb=3.2v efficiency (%) 40 50 60 70 80 90 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) vb=1.0v vb=1.3v vb=2.0v vb=2.6v vb=3.2v efficiency (%) 40 50 60 70 80 90 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) vb=1.0v vb=1.3v vb=2.0v vb=2.6v vb=3.2v efficiency (%) 40 50 60 70 80 90 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) vb=1.0v vb=1.3v vb=2.0v vb=2.6v vb=3.2v efficiency (%) 3.27 3.28 3.29 3.30 3.31 3.32 3.33 020406 080 100 120 140 160 180 200 iload (ma) vb=1.3v vb=2.6v v out (v) 3.27 3.28 3.29 3.30 3.31 3.32 3.33 010203 04050607080 90100 iload (ma) vb=1.3v vb=2.6v v out (v) performance characteristics
5 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation refer to the circuit in figure 28, t amb = +25 o c unless otherwise noted. figure 11. maximum load current vs. vbatt (vout=3.3v), li=22uh sumida cd43 figure 13. no load battery current vs. vbatt (vout=3.3v), li=22uh sumida cd43 figure 14. output voltage vs. temperature, rlim=2.5k, rload=3k, (vout=3.3v),li=22uh sumida cd43 figure 16. ibatt pin quiescent current vs. temperature, (vout=3.3v), vbatt=1.0v figure 15. io pin quiescent current vs. temperature, (vout=3.3v) figure 9. line/load vs. output current (vout=5v), rlim=2.5k, li=22uh sumida cd43, refer to figure 29, r1=499k, r2=169k figure 10. line/load vs. output current (vout=5v), rlim=5k, li=22uh sumida cd43, refer to figure 29, r1=499k, r2=169k figure 12. maximum load current vs. vbatt (vout=5v), li=22uh sumida cd43, refer to figure 29, r1=499k, r2=169k 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 010203 0405060708090100 iload (ma) vb=1.3v vb=2.6v v out (v) 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 010203 04050 iload (ma) vb=1.3v vb=2.6v v out (v) 0 20 40 60 80 100 120 140 160 180 200 220 240 0.0 1.0 2.0 3.0 4.0 vbatt (v) rlim=2.5k rlim=5k max i o (ma) 0 20 40 60 80 100 120 140 160 180 200 220 240 0.0 1.0 2.0 3.0 4.0 vbatt (v) rlim=2.5k rlim=5k max i o (ma) 10 100 1000 10000 0.0 1.0 2.0 3.0 4.0 vbatt (v) rlim=2.5k rlim=5k battery current ( a) 3.27 3.28 3.29 3.30 3.31 3.32 3.33 -40 -20 0 20 40 60 80 100 temperature (degc) v out (v) 30 35 40 45 50 55 60 -40 -20 0 20 40 60 80 100 temperature (degc) i oq ( a) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -20 0 20 40 60 80 100 temperature (degc) i bq ( a) performance characteristics
6 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation figure 17. sp6644/6201 dc/dc ldo combination efficiency vs. output current (vout=3.3v), rlim=2.5k, li=22 h sumida cd-43, refer to figure 30 figure 18. sp6644/6201 ldo line/load rejection vs. output current (vout=3.3v), rlim=2.5k, li=22 h sumida cd-43, refer to figure 30 figure 19. sp6644/6201 dc/dc ldo maximum load current vs. vbatt (vout=3.3v), rlim=2.5k, li=22 h sumida cd-43, refer to figure 30 figure 20. sp6644/6201 dc/dc ldo no-load ibatt vs. vbatt (vout=3.3v), rlim=2.5k, li=22 h sumida cd- 43, refer to figure 30 figure 21. sp6644/6201 dc/dc ldo output ripple voltage (vout=3.3v), rlim=2.5k, li=22 h sumida cd- 43, refer to figure 30 figure 22. load transient response, vbatt=1.3v, (vout=3.3v), rlim=2.5k, li=22 h sumida cd-43 figure 23. line transient response, (vout=3.3v), rlim=2.5k, iload=22 h sumida cd-43 figure 24. switching waveforms, (vout=3.3v), vbatt=1.3v, rlim=2.5k, iload=10ma, li=22 h sumida cd-43 refer to the circuit in figure 28, t amb = +25 o c unless otherwise noted. 30 40 50 60 70 80 90 100 0.1 1.0 10.0 100.0 1000.0 iload (ma) vb=1.0v vb=1.3v vb=2.0v vb=2.6v vb=3.2v efficiency (%) 3.032 3.033 3.034 3.035 3.036 3.037 020406 080 100 120 140 160 180 200 iload (ma) vb=1.3v vb=2.6v v out (v) 0 20 40 60 80 100 120 140 160 180 200 220 240 0.0 1.0 2.0 3.0 4.0 vbatt (v) max i o (ma) 10 100 1000 10000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 vbatt (v) battery current ( a) sp6201 out 10mv/div sp6644 out 20mv/div li 0.5a/div v out 50mv/div v batt 50mv/div v out 50mv/div v batt 1v/div li 0.2a/div v out , v lx ,v batt 1v/div performance characteristics
7 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation figure 25. shutdown response and inductor current, vout=3.3v, vbatt=1.3v, rlim=2.5k, rload=550 ohms, li=22uh sumida cd43 table 1. sp6644/6645 pin descriptions figure 26. pinout for the sp6644/6645 refer to the circuit in figure 28, t amb = +25 o c, unless otherwise noted. v out gnd rlim v batt lx 1 2 3 4 5 6 7 8 sp6644 sp6645 shdn fb battlo e m a nn o i t c n u f. o n n i p v t t a b . r o t a r a p m o c o l t t a b e h t f o t u p n i r o s n e s e h t o t s e i t n i p s i h t . y l p p u s y r e t t a b 1 o l t t a b e h t r o f v 1 w o l e b s p o r d e g a t l o v e h t n e h w . t u p t u o w o l y r e t t a b n i a r d - n e p o 4 4 6 6 p s r o e h t r o f v 2 5 4 6 6 p s . t n e r r u c s k n i s o l t t a b , 2 r m i l o t n i p s i h t m o r f r o t s i s e r a g n i t c e n n o c . t n e r r u c k a e p r o t c u d n i e l b a m m a r g o r p r o t s i s e r e r e h w t n e r r u c k a e p r o t c u d n i e h t s m a r g o r p d n u o r g 3 n d h sv o t t c e n n o c . t u p n i n w o d t u h s w o l - e v i t c a t t a b . n o i t a r e p o l a m r o n r o f4 b f n a o t n i p t u p n i s i h t t c e n n o c . n o i t a r e p o t u p t u o - e l b a t s u j d a r o f t u p n i . t u p n i k c a b d e e f v n e e w t e b r e d i v i d e g a t l o v r o t s i s e r l a n r e t x e t u o - d e x i f r o f d n g o t t c e n n o c . d n g d n a . n o i t a r e p o t u p t u o 5 d n g. d n u o r g y l l a c i p y t , l a i t n e t o p t i u c r i c t s e w o l e h t o t t c e n n o c 6 x l v m o r f d e t c e n n o c s i r o t c u d n i n a . l i o c t t a b d n a n i a r d h c t i w s t e f s o m l e n n a h c - n e h t o t . n i p s i h t h g u o r h t n i a r d r e i f i t c e r - s u o n o r h c n y s l e n n a h c - p e h t 7 v t u o t c e n n o c . t u p n i r e w o p c i d n a n o i t a r e p o v 3 . 3 d e x i f r o f t u p n i k c a b d e e f . t u p t u o r e w o p v o t e s o l c r o t i c a p a c r e t l i f t u o . 8 i peak = 1400 r lim sdn 2v/div li 0.5a/div v out , v batt 1v/div performance characteristics pin description
8 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation description the sp6644/6645 devices are high-efficiency, low-power step-up dc-dc converters ideal for single or dual alkaline cell applications such as pagers, remote controls, and other low-power portable end products. the sp6644/6645 devices feature a 5na logic- controlled shutdown mode and a dedicated low-battery detector circuitry. both devices contain a 0.8 ? synchronous rectifier, a 0.5 ? n-channel mosfet power switch, an internal voltage reference, circuitry for pulse-frequency- modulation, and an under voltage comparator. the output voltage for the sp6644/6645 devices can be adjusted from +2v to +5.5v by manipulating two external resistors. the output voltage is preset to +3.3v. theory of operation the sp6644/6645 devices are ideal for end products that function with a single or dual alkaline cell, such as remote controls, pagers, and other portable consumer products. designers can implement the sp6644/6645 devices into applications with the following power management operating states: 1. where the primary battery is good and the load is active, and 2. where the primary battery is good and the load is sleeping. in the first operating state where the primary supply is good and the load is active, the sp6644/6645 devices typically offer 88% efficiency, drawing tens of milliamps. applications will predominantly operate in the second state where the primary supply is good and the load is sleeping. the sp6644/6645 devices draw a very low quiescent current while the load in its disabled state will draw typically hundreds of microamps. the pulse-frequency-modulation (pfm) circuitry provides higher efficiencies at low to moderate output loads than traditional pwm converters are capable of delivering. in a state where the error comparator detects that the output voltage at v out is too low, the internal n-channel mosfet switch is turned on until the peak inductor current is satisfied. this is indicated by the falling edge of the i-charge comparator output. the approximate inductor charging time is defined by: t charge ? ? ? ? ? l x i peak / v batt where t charge [s] is the approximate inductor charging time, l [h] is the inductance, i peak [a] is the peak inductor current, and v batt [v] is the input voltage to the device. the peak inductor current, i peak , is programmed externally by putting a resistor between the r lim pin and ground. this is defined by: i peak = 1400 r lim where i peak [a] is the peak inductor current and r lim [ ? ] is the value of the resistor connected from pin r lim to ground. when the charging n mosfet turns off, the discharging p mosfet turns on and the inductor current flows into the output capacitor and the load recharging the output. when the current through the discharging p mosfet approaches zero, the i-discharge comparator indicates to the logic to turn off the p mosfet. the approximate time for discharging the inductor current can be determined by: t dchg ? ? ? ? ? l x i peak v out - v batt where t dchg [s] is the time to discharge the inductor, l [h] is the inductance, i peak [a] is the peak inductor current, v out [v] is the output voltage, and v batt [v] is the input voltage to the device. the output filter capacitor stores charge while current from the inductor is high and holds the output voltage high until the discharge phase of the next switching cycle, smoothing power flow to the load. between switching cycles, the inductor damping switch is closed suppressing the ringing caused by the inductor and the parasitic capacitance on the lx node.
9 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation figure 27. internal block diagram of the sp6644/6645 shdn logic drv-p drv-n fb v batt p discharge v out lx +1.0v ( sp6644 ) +2.0v ( sp6645 ) v ref battlo start up osc n charge n sp6644 sp6645 n inductor damping switch i-discharge i-charge refready +1.0v ( sp6644 ) +2.0v ( sp6645 ) v lpk gnd +1.25v r lim r lim block diagram
10 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation internal bootstrap circuitry the internal bootstrap circuitry contains a low-voltage start-up oscillator that pumps up the output voltage to approximately 1.9v so the main dc-dc converter can function. at lower battery supply voltages, the circuitry can start up with low-load conditions. designers can reduce the load as needed to allow start-up with input voltages below 1v. refer to figures 10 to 13 . once started, the output voltage can maintain the load as the battery voltage decreases below the initial start-up voltage. the start-up oscillator is powered by v batt driving a charge pump and nmos switch. during start-up, the p-channel synchronous rectifier remains off and either its body diode or an external diode is used as an output rectifier. battlo circuitry the sp6644 device has an internal comparator for low-battery detection. if v batt drops below 1v, battlo will sink current. battlo is an open-drain output. the sp6645 operates in the same manner with a threshold voltage of 2v. shutdown for the sp6644 a logic low at shdn will drive the sp6644 into a shutdown mode where battlo goes into a high-impedance state, the internal switching mosfet turns off, and the synchronous rectifier turns off to prevent reverse current from flowing from the output back to the input. designers should note that in shutdown, the output can drift to one diode drop below v batt because there is still a forward current path through the synchronous-rectifier body diode from the input to the output. to disable the shutdown feature, designers can connect shdn to v batt . adjustable output voltage driving fb to ground (logic low) will drive the output voltage to the fixed-voltage operation of +3.3v + 4%. connecting fb to a voltage divider between v out and ground will select an adjustable output voltage between +2v and +5.5v. refer to figure 28 . fb regulates to +1.25v. since the fb leakage current is 10na maximum, designers should select the feedback resistor r2 in the 100k ? to 1m ? range. r1 can be determined with the following equation: r1 = r2 x -1 v out v ref where r1 [ ? ] and r2 [ ? ] are the feedback resistors in figure 29 , v out [v] is the output voltage, and v ref [v] is 1.25v. battery reversal protection the sp6644/6645 devices will tolerate single- cell battery reversal up to the package power- dissipation limits noted in the absolute maximum ratings section. an internal diode in series with an internal 5 ? resistor limits any reverse current to less than 220ma preventing damage to the devices. prolonged operation above 220ma reverse-battery current can degrade performance of the devices. the inductor the programmable peak inductor current feature of the sp6644/6645 devices affords a great deal of flexibility in choosing an inductor. the most important point to consider when choosing an inductor is to insure that the peak inductor current is programmed below the saturation rating of the inductor. if the inductor goes into saturation, the internal switches and the inductor will be stressed due to current peaking, potentially leading to reliability problems with the application circuit. the peak inductor current is programmed by putting a resistor between the r lim pin and ground. the usable current range is between 150ma and 560ma. this is defined by: where i peak [a] is the peak inductor current, and r lim [ ? ] is the value of the resistor connected from pin r lim to ground. i peak = 1400 r lim
11 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation with an external resistor tolerance of +1%, the peak current tolerance will be +6%. to make sure that the sp6644/6645 internal circuitry adequately controls the inductor current, it is recommended that values equal to or greater than 22 h ( + 10%) be used. the sp6644/6645 devices control algorithm delivers an average maximum load current in regulation as defined by: where i load-max [a] is the maximum load current, e is the efficiency factor (generally between 0.8 and 0.9), i peak [a] is the programmed peak inductor current, v batt [v] is the input voltage to the device, and v out [v] is the output voltage. given the minimum input voltage, output voltage, and maximum average load current, the value of i peak can be solved for and an appropriate inductor can be chosen. it is good design practice to use the lowest peak current possible to reduce possible emi and output ripple voltage. a closed-core inductor, such as a toroid or shielded bobbin, will minimize any fringe magnetic fields or emi. figure 28. adjustable output voltage circuitry application notes printed circuit board layout is a critical part of design. poor designs can result in excessive emi on the voltage gradients and feedback paths on the ground planes with applications involving high switching frequencies and large peak currents. excessive emi can result in instability or regulation errors. all power components should be placed on the pc board as closely as possible with the traces kept short, direct, and wide ( >50mils or 1.25mm). extra copper on the pc board should be integrated into ground as a pseudo-ground plane. on a multilayer pc board, route the star ground using component-side copper fill, then connect it to the internal ground plane using vias. for the sp6644/6645 devices, the inductor and input and output filter capacitors should be soldered with their ground pins as close together as possible in a star-ground configuration. the v out pin must be bypassed directly to ground as close to the sp6644/6645 devices as possible (within 0.2in or 5mm). the dc-dc converter and any digital circuitry should be placed on the opposite corner of the pc board as far away from sensitive rf and analog input stages. the external voltage-feedback network should be placed very close to the fb pin as well as the r lim resistor (within 0.2in or 5mm). any gnd v out fb lx v batt 47 f 0.1 f 22 f r lim v out = 2v to 5.2v shdn 0.88v to 3.3v input sp6644 sp6645 100pf* r1 r2 *optional compensation 22 h 0.7a battlo i load-max = e x i peak x v batt 2 x v out
12 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation noisy traces, such as from the lx pin, should be kept away from the voltage-feedback network and separated from it using grounded copper to minimize emi. capacitor equivalent series resistance is a major contributor to output ripple, usually greater than 60%. low esr capacitors are recommended. ceramic capacitors have the lowest esr. low-esr tantalum capacitors may be a more acceptable solution having both a low esr and lower cost than ceramic capacitors. designers should select input and output capacitors with a rating exceeding the peak inductor current. do not allow tantalum capacitors to exceed their ripple-current ratings. a 22 f, 6v, low-esr, surface-mount tantalum output filter capacitor typically provides 60mv output ripple when stepping up from 1.3v to 3.3v at 20ma. an input filter capacitor can reduce peak currents drawn from the battery and improve efficiency. low-esr aluminum electrolytic capacitors are acceptable in some applications but standard aluminum electrolytic capacitors are not recommended. designers should add lc pi filters, linear post-regulators, or shielding in applications necessary to address excessive noise, voltage ripple, or emi concerns. the lc pi filter's cutoff frequency should be at least a decade or two below the dc-dc converters's switching frequency for the specified load and input voltage. a small sot23-5pin 200ma low drop out linear regulator can be used at the sp6644/6645 output to reduce output noise and ripple. the schematic in figure 29 illustrates this circuit with the sp6644 3.3v output followed by the sipex sp6201 3.0v output low drop out linear regu- lator. compare in figure 21 the sp6644 ripple of 40-50mvpp with the sp6201 ripple of about 3mvpp and you can see the amount of noise reduction obtained. additional performance characteristics for the sp6644/6201 combina- tion can be seen in figures 17 to 20. table 1. surface-mount inductor information inductor specification inductance manufacturer/part no. resistance isat (uh) (ohms) (ma) sumida cd43-220 0.38 (max) 680 22 sumida cdrh5d18-220 0.28 (max) 760 coilcraft do1608c-223 0.32 (typ) 700 47 sumida cd43-470 0.84 (max) 440 coilcraft do1608c-473 0.56 (typ) 500 100 sumida cd54-101 0.7 (max) 520 coilcraft do1608c-104 1.1(typ) 310
13 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation figure 29. schematic sp6644/6201 dc/dc ldo combination 0.88v to 3.3v input v batt gnd battlo shdn c1 47 f j1 1 2 3 r3 2.5k probe access points for external connection by the user r2 100k r1 open l1 22 h +3.3v v out c2 47 f +3.0v v out c3 1 f sp6201 gnd sp6644 u1 v batt r lim battlo shdn v out gnd lx fb r4 1m lx + + v in gnd enable reset_n v out 1 2 3 4 5 7 6 8 1 2 3 4 5 schematic with ldo combination
14 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation package: 8 pin msop l1 l r1 1 r 1 seating plane 1 e1 2 e/2 e d gauge plane l2 pin #1 indentifier must be indicated within this shaded area (d/2 * e1/2) e a2 a a1 b e1 b b symbol min nom max a-- 1.1 a1 0 - 0.15 a2 0.75 0.85 0.95 b 0.22 - 0.38 c 0.08 - 0.23 d e e1 e e1 l 0.4 0.6 0.8 l1 l2 n-8- r 0.07 - - r1 0.07 - - ?0o-8o ?1 0o - 15o note: dimensions in (mm) 0.65 bsc 1.95 bsc 0.95 ref 0.25 bsc 8 pin msop jedec mo-187 (aa) variation 3.00 bsc 4.90 bsc 3.00 bsc c with plating base metal b section b-b
15 date: 11/30/04 sp6644/6645 high efficiency boost regulator ?copyright 2004 sipex corporation part number temperature range package type sp6644eu ............................................. -40 o c to +85 o c ......................................... 8-pin msop sp6644eu/tr ....................................... -40 o c to +85 o c ......................................... 8-pin msop sp6645eu ............................................. -40 o c to +85 o c ......................................... 8-pin msop sp6645eu/tr ....................................... -40 o c to +85 o c ......................................... 8-pin msop corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com ordering information /tr = tape and reel pack quantity is 2500 for msop. available in lead free packaging. to order add "-l" suffix to part number. example: sp6644eu/tr = standard; sp6644eu-l/tr = lead free

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